1. Field of the Invention
The present invention generally relates to a method of making integrated circuit (IC) chips to substrates and, more particularly, to a process which provides a protecting resist of a ball limiting metal (BLM) during etch process resulting in the formation of an ideal contact structure.
2. Description of the Prior Art
In recent years, several methods of making integrated circuit chip to substrate connections have been developed. A well-known technique for connecting the chip to a carrier is the Controlled Collapse Chip Connection (C-4) technique developed by the International Business Machines Corp. (IBM) which allows a plurality of input/output (I/O) terminals to be close together. Another well-known technique for packaging chips or carriers is the Tape Automated Bonding (TAB) technique. TAB packaging involves the use of a web of material to carry, electrically conductive leads which provide connections between the chip and the outside world. Another method is to use a molybdenum mask containing holes in the appropriate locations and to evaporate successive layers of chromium (Cr), copper (Cu) and gold (Au) and a lead/tin (PbSn) solder through the mask onto the wafer.
The conventional methods of forming the metal bumps on a semiconductor substrate has the shortcoming that the bonding force of the bumps on the substrate is not sufficient, because the etchant used in the process etches the electrode pads. U.S. Pat. No. 4,293,637 to Hatada et al. discloses an improvement in which strong metal bumps are made, undesirable etching of external lead wires of the semiconductor device is avoided, and metal bumps of substantially uniform height even on different kinds of regions are made.
U.S. Pat. No. 4,273,859 to Mones et al. provides an improved method of forming raised input/output terminals, or I/O bumps, on the top surface of integrated circuits (IC) chips while the IC chips are still integral; i.e., IC elements of a single crystal silicon wafer.
U.S. Pat. No. 5.010,389 to Gansauge et al. relates to the packaging of electronic components on a carrier, preferably on a silicon carrier, and particularly to an IC chip packaging structure which comprises on a substrate different terminals for different packaging or connection techniques.
Japanese Application Nos. 63-18665 and 57-226135 show semiconductor devices in which barrier metals are "stepped" to strengthen contact ball connection.
U.S. Pat. No. 4,861,425 to Greer et al. shows one of the lift-off processes in the art of semiconductor terminal metallurgy, which provides an improved method for the formation and fabrication of terminal metallurgy of integrated circuits. A process is described for selective removal of unwanted metallization from the surface of a semiconductor device.
Another method of forming thin film patterns in the fabrication of integrated circuits utilizing a lift-off mask is shown in U.S. Pat. No. 4,272,561 issued to Rothman et al. This invention relates to a method of depositing thin films, particularly thin films such as metallic films, in the fabrication of integrated circuits.
U.S. Pat. No. 5,027,188 to Owada et al. shows a semiconductor integrated circuit device and, more particularly, a technique which is useful when applied to a semiconductor integrated circuit device of a so-called "flip-chip" system in which a semiconductor chip is mounted to a substrate through solder bumps.
While the art IC chip to carrier connections is well developed, as represented by prior art described above, there remain some problems inherent in this technology. These problems include the etching of one metal in the presence of others, all of which have different electrochemical potentials and anodic reactions, the creation of a stepped structure, and the alignment of the exposure mask.